In 1921, E. L. Post in the American Journal of Mathematics, in a paper entitled "Introduction to a General Theory of Elementary Propositions" proposed an n-valued logic as a generalization of the algebra of elementary propositions. Since then considerable work has proceeded with the synthesis of n-valued switching circuits.
Considerable advantages may be gained by considering systems of a radix higher than 2 and built from multiple-valued elements. They may show increased speed of arithmetic operation because of the smaller number of digits required for a given accuracy, assuming that multiple-valued logic elements can operate at a speed approaching that of the corresponding binary logic elements. They can permit a better utilization of transmission channels because of the higher information content carried by each line. They have more efficient error detection and correction codes. They possess higher density of information storage. They offer some reduction of wiring complexity which is an important factor in the area of integrated circuit technology.
Three-valued logic, which is a special case of the multiple-valued logic, has an attractive interest since the classical calculus shows that the most efficient representation of numbers is with the base e(2.71828 . . .), and 3 is the nearest integer to it. Moereover, in digital-computer process control the required outputs are basically ternary, e.g. for a digital shaft servo three commands are needed: No error, remain in position; anticlockwise error, rotate clockwise; and clockwise error, rotate anticlockwise.
Due to some properties of Complementary-Symmetry Metal Oxide Semiconductor Devices, known as CMOS (or COS/MOS) integrated circuits, one may use them in the design of ternary logic circuits, of course in a way which differs somewhat from normal binary logic circuit designs. Two resistors are inserted between two channel transistors of complementary type. The added resistors permit one to obtain three equiprobable stable voltage levels when two power supplies are used to ensure proper biasing. One of the power supplies is positive and is applied to the source of the p-channel transistor (V.sub.DD = V), and the second one is negative, with value V.sub.SS = -.vertline.V.sub.DD .vertline. = -V applied to the source of the n-channel transistor. The three voltage levels are then equal to V, zero potential and -V. Based on this idea the ternary inverters, NAND and NOR are realized with the CMOS integrated circuits.
With the advancing electronic technology, interest in multi-valued logic, and especially in the ternary one, has grown rapidly. Much work has been done on ternary combinational logic circuits, but few studies have been centered on the design of ternary sequential circuits. This may be attributed to the lack of suitable ternary memory elements. The use of integrated circuits in designing ternary memory elements may be a good solution to this problem.
Because of some properties of CMOS (or COS/MOS) devices, they may be used in the design of ternary logic circuits, in a manner which differs somewhat from the design of normal or ordinary binary logic circuits. Therefore, according to this invention, ternary memory circuits are designed using CMOS (or COS/MOS) integrated circuits; and this is accomplished by means of ternary operators and fundamental circuits. Several ternary sequential circuits and memory matrix operators are then constructed using the basic ternary logic operators and memory elements of this invention.
All of the circuits presented herein have been realized using CD4007AE and Quad Bilateral Switch CD4016AE RCA COS/MOS integrated circuits. The first chip comprises three p-channel and three n-channel enhancement-type MOS transistors; and the second chip comprises four independent bilateral signal switches, each of which consists of a p-channel and an n-channel device.